Recent advances in integrated circuit manufacturing technology have enabled the implementation of higher numbers of transistors on single integrated circuit chips, and also have increased their performance, especially for high density synchronous circuits, such as microprocessors, math co-processors, single-chip microcomputers and the like. Such higher performance is generally obtained from synchronous circuits by increasing the frequency of the clock signal controlling the circuit. For example, the microprocessors in modern personal computers and workstations currently operate at clock frequencies of up to 40 MHz, with higher frequencies expected to follow.
Particularly at extremely high clock frequencies, parasitic impedances, propagation delays, and other effects can cause the clock signals that are applied to different integrated circuits within a computer to be skewed in time relative to one another. As a result, inter-chip communication within such computers is made more difficult at higher frequencies, requiring wait states or other techniques to be used to reliably communicate data. The synchronization of multiple chips thus tends to degrade the rate at which data can be communicated within the system, and thus degrading overall system performance. In addition, high frequency clock signals are especially vulnerable to certain instabilities in their duty cycle, to noise, ringing, and other similar effects, each of which may cause errors in the internal operation of the integrated circuits receiving such signals.
Phase-locked loops (PLLs) are conventionally implemented onto integrated circuits to overcome these problems. As is fundamental in the art, a PLL consists of a phase detector circuit, a low pass loop filter, and a voltage controlled oscillator (VCO). The phase detector circuit compares the phase of the input clock signal with the output of the VCO, and presents a control voltage to the VCO (after filtering by the loop filter) to adjust the frequency of the output signal. After several cycles, the PLL locks onto the input clock signal, and presents an output having a stable frequency and phase. A frequency divider may be connected to the output of the VCO, depending upon the VCO free-running frequency, so that the PLL output frequency matches that of the input clock signal. In addition, as is well known, frequency dividers in the output and feedback loops of the PLL can also allow frequencies other than that of the input clock signal to be generated. U.S. Pat. No. 4,931,748, issued Jun. 5, 1990, describes an implementation of one example of a phase-locked loop in an integrated circuit such as a microprocessor.
A particularly useful type of PLL for high speed integrated circuits is the charge-pump PLL. As described in Gardner, "Charge-Pump Phase-Lock Loops", IEEE Trans. Commun., Vol. COM-28 (November 1980), pp. 1849-1858, a charge pump may be provided to charge or discharge a capacitor in the loop filter according to the polarity of the phase difference between the input clock signal and the output signal. FIG. 2b of this reference illustrates a typical implementation of a charge-pump loop filter, where the phase detector generates an up (U) signal or a down (D) signal according to the polarity of the phase difference, and where the charge pump connects either a charging or a discharging current source to the capacitor according to the U and D signals. A conventional phase detector for generating the U and D signals is described in Jeong et al., "Design of PLL-Based Clock Generation Circuits", IEEE J. Solid State Circ., Vol. SC-22, No. 2 (April, 1987), pp. 255-261.
In the art of PLL-based clock generation, one must generally tradeoff fast response of the PLL to a new input clock frequency, on one hand, with frequency stability, on the other hand. By way of further background, U.S. Pat. No. 4,771,249, issued Sep. 13, 1988, describes a charge-pump PLL having a wide-bandwidth mode and a narrow-bandwidth mode. The charge pump disclosed in this reference includes a current mirror which sets a fixed current in an output leg based on a fixed current in a reference leg. In the wide-bandwidth mode, the charge pump is controlled to switch in an additional output leg to source or sink additional current; the additional output leg is switched out in the narrow-bandwidth mode. Control of the switching in and out of the additional output leg is disclosed as being dependent on the output frequency varying above and below the desired frequency a predetermined number of times. By way of further background, U.S. Pat. No. 4,920,320, issued Apr. 24, 1990, discloses a circuit for stabilizing the switching operation in the charge-pump PLL disclosed in the above-referenced U.S. Pat. No. 4,771,249.
By way of further background, U.S. Pat. No. 4,745,372 describes a PLL clock generator circuit including a current-variable charge pump operable in modes having different bandwidths, depending upon a phase lock signal generated by the phase comparator. As shown in FIGS. 10 and 11 of this reference, in one disclosed embodiment, two current mirrors are used to control the rate at which charging and discharging of the pumped output node, according to complementary signals generated by integrating the phase lock signal.
By way of further background, passive loop filters in conventional PLLs generally require the use of a sufficiently large capacitor that integration of the capacitor into the PLL integrated circuit is not practicable. As such, conventional PLLs generally require an external capacitor to be connected to a terminal of the circuit. Such use of an external capacitor is, of course, generally undesirable due to the increased manufacturing cost, the incrementally increasing likelihood of failure due to an additional connection, and the effects of the additional parasitic inductance of the external connection, especially at high frequencies. Furthermore, variations in the capacitance value of an external component will generally not match variations in the manufacture of the integrated circuit, and thus the performance characteristics of such PLLs may widely vary.
It is an object of the present invention to provide a fully-integrated charge pump PLL having a fast response time to input frequency changes as well as highly stable behavior in the phase-locked condition.
It is a further object of the present invention to provide such a circuit which has selectably variable response times in the loop filter.
It is a further object of the present invention to provide such a circuit in which the slew rate of the loop filter is controlled according to the relationship between the input and feedback clock signals.
It is a further object of the present invention to provide such a circuit which is especially useful for high frequency operation.
It is a further object of the present invention to provide such a circuit which may be efficiently implemented into the integrated circuit.
It is a further object of the present invention to provide such a circuit which may have several selectable response rates.
It is a further object of the present invention to provide such a circuit in which the bandwidth may be selected independently of the polarity of the desired change in output clock frequency.
It is a further object of the present invention to provide such a circuit which may be selectably enabled and disabled.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.